The present invention relates to a decision-feedback equalizer for use in an input buffer. In particular, the present invention relates to implementations of decision-feedback equalizers with improved power efficiency, increased bandwidth and reduced circuit area.
Today's data networks require high-speed data communication with serial link data rates of more than 10 Gbit/s. In this bandwidth range, a further increase of serial link data rates is challenging due to the limited general bandwidth. The general bandwidth is usually determined by dielectric losses and reflections on the transmission channel which result in a widening of the transmitted signal pulses over more than one unit interval, so that the received signal is distorted by intersymbol interference.
These signal distortions are usually compensated for by means of equalizing functions in the receiving circuitry, such as feed-forward equalizing and decision-feedback equalizing. A decision-feedback equalizer (DFE) is capable of reducing signal distortions while leaving noise or cross-talk unaffected.
In general, a decision-feedback equalizer is included in the digitalized data path at an output side of an analog-digital converter and is substantially configured to compensate for the effects of one transmitted pulse onto one or more succeeding pulses of the incoming stream of digitalized data samples. The general concept of a decision-feedback equalizer implementation is to provide at least one comparator used to translate the single pulses of the stream of digitalized data samples into a bit stream. In the comparator, the digitalized data samples are each compared with a respective variable threshold value, which may be generated depending on the history of (preceding) data samples tapped from the output of the decision-feedback equalizer. The variable threshold value is obtained by delaying the bit outputs of the decision-feedback equalizer for one or more clock cycles in a number of delay stages by weighting each of the delayed bit outputs of the decision-feedback equalizer after each stage by a predetermined (preset) coefficient and by then adding the results. The coefficients are preset with respect to a standard pulse response of the specific transmission channel. In particular, the adding-up of the weighted delayed DFE outputs requires adding circuits which usually have a relatively high power and area consumption in an integrated circuit implementation.
An additional approach, known as speculation or loop-unrolling, is to precompute the variable threshold values for each pattern of delayed DFE bit outputs. Speculation or loop-unrolling for DFE is a technique that implements all possible rated summations at the output of a finite impulse response (FIR) filter in the DFE feedback path in order to reduce the critical path time of the DFE coefficients' summation time. All possible combinations of N post-cursors (N taps) intersymbol interference terms are accordingly generated in a speculative decision-feedback equalizer of the order N, so that a total of 2N combinations or speculations are generated. The correct decision is selected among the 2N speculations on the basis of the last N decisions. This approach should help to save area and power impact of the line of adding circuits. However, hardware complexity grows exponentially with the number N of taps, i.e. the number of considered historical data samples. As for each of the threshold values a separate comparator latch is needed, the output of which are to be selected by a multiplexer, the overall circuitry has the disadvantage of requiring a large circuit area and having a high power consumption.
Document U.S. Pat. No. 7,792,187 B2 discloses a decision-feedback equalizer comprising summer circuits configured to add a dynamic feedback signal representing a dynamic feedback tap to a received input and to speculate on a speculative tap; data slicers configured to receive outputs of the summer circuits and sample the outputs of the summer circuits in accordance with a clock signal; first multiplexers, each configured to receive a first input from a corresponding data slicer; and second multiplexers, each configured to receive an output of a plurality of first multiplexers, the second multiplexers having an output fed back to a second input of the first multiplexers and the second multiplexer output being employed to provide a select signal for a second multiplexer on a different section of the DFE and to drive the dynamic feedback signal to a summer circuit on a same section of the DFE. This approach provides that a slave latch of a conventional master-slave flip-flop is replaced by a multiplexer driven by a half-rate clock.
Document US 2013/0322512 A1 discloses a decision-feedback equalizer (DFE) slicer for a receiver, comprising a plurality of non-speculative DFE taps; and 3 speculative DFE taps, wherein the 3 speculative DFE taps comprise first and second multiplexer stages. Each of the first and second multiplexer stages comprises 4 comparator latches, each of which has a programmable offset; and a multiplexer that receives 4 comparator latch outputs from the 4 comparator latches and outputs a multiplexer stage output, wherein the multiplexer is controlled by previous symbol decisions dn-2 and dn-3, wherein the previous symbol decisions dn-2 and dn-3 are received from two other respective DFE slices in the receiver. The 3 speculative taps further comprise a 2:1 decision multiplexer stage that receives the multiplexer stage outputs of the first and second multiplexer stages and is controlled by a previous symbol decision dn-1 received from a third respective DFE slice in the receiver to output a slice output signal dn.
Document Payandehnia, P. et al “A 4 MW 3-TAP 10 GB/S DECISION-FEEDBACK EQUALIZER”, IEEE Date: 7-10 Aug. 2011 relates to a half-rate low-power 3-tap decision-feedback equalizer with an improved switched-capacitor-based summer architecture for speculating the first feedback tap. The other two taps are cancelled using a current summation technique. Further power consumption reduction is achieved by using a sense-amplifier-based slicer and a pass-gate multiplexer.